(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an improved buried contact without a trench in the fabrication of integrated circuits.
(2) Description of the Prior Art
FIGS. 1-3 illustrate the typical buried contact process of the prior art. FIG. 1 illustrates a partially completed integrated circuit device. Field oxide regions, such as 12, are formed in and on the semiconductor substrate 10. A gate oxide layer 14 is grown upon the surface of the substrate. Typically, a so-called "split poly" process is used wherein a first layer of polysilicon 16 is deposited over the gate oxide layer to protect the gate oxide from the photoresist process. A layer of photoresist is coated over the polysilicon layer 16 and patterned to form the photoresist mask 20.
The polysilicon and gate oxide layers are etched away where they are not covered by the photoresist mask to form an opening where the buried contact is to be formed. As illustrated in FIG. 2, the second layer of the split poly 22 is deposited over the first polysilicon layer and within the opening. A second photoresist mask 24 is formed over the substrate.
Referring now to FIG. 3, dopant from the polysilicon layer 22 is driven in to form the buried contact 26 and the polysilicon and gate oxide layers are etched to form gate electrode 28 and polysilicon interconnection line 30. Source/drain regions 32 are formed.
As device dimensions and cell size continue to decrease for high density and improved performance in integrated circuits, there is a growing demand for lower junction leakage and lower contact resistance. However, the contact resistance and junction leakage will increase in the conventional buried contact process if there is misalignment of the photoresist mask during polysilicon etching.
FIG. 4 illustrates the case in which the photoresist mask 24 is shifted to the left. Buried contact trench 35 is formed. This causes an increase in both contact resistance and leakage current. FIG. 5 illustrates the case in which the photoresist mask is shifted to the right. A disconnection gap 37 is left between the buried contact 26 and the source/drain region 32. This increases contact resistance by causing a high series resistance. The dotted lines in each figure illustrates the current path.
A number of patents disclose methods for improving a device in which a buried contact trench has been formed. For example, U.S. Pat. No. 5,525,552 to J. M. Huang teaches the use of a low dielectric constant spacer to provide better immunity of the buried contact trench. U.S. Pat. No. 5,607,881 also to J. M. Huang teaches linking the buried contact junction and the source junction by an extra high dosage N+ implant to overcome the disadvantages of a buried contact trench. U.S. Pat. No. 5,668,051 to Chen et al teaches a thin polysilicon layer within the buried contact trench. U.S. Pat. No. 5,652,152 to Pan et al discloses the use of a PSG spacer to solve the buried contact trench problem.
Other patents teach methods to avoid forming a buried contact trench. For example, U.S. Pat. No. 5,494,848 to H. W. Chin teaches the use of a reverse tone oversized buried contact mask to prevent formation of a buried contact trench. U.S. Pat. No. 5,654,231 to M. S. Liang et al teaches the use of sidewall spacers to prevent the formation of a buried contact trench in DRAM technology. Co-pending U.S. patent application Ser. No. 09/035,139, now U.S. Pat. No. 5,998,269 issued on Dec. 7, 1999 (TSMC-97-305) to K. C. Huang et al teach a method of forming polysilicon gate electrodes and interconnection lines before forming a buried contact and depositing a refractory material layer over the buried contact.
Still other patents teach other buried contact processes. For example, U.S. Pat. No. 5,332,913 to Shappir discloses a buried interconnect structure in which a contact is formed over a field oxide region. A poly-epi silicon layer is formed over the contact and another oxidation region is formed over the poly-epi silicon layer. U.S. Pat. No. 5,543,362 to Wu teaches a process in which a silicide layer is deposited over the buried contact region followed by a polysilicon layer and topped with a second silicide layer. U.S. Pat. No. 5,162,259 to Kolar et al teaches forming a silicide over the buried contact region and depositing polysilicon overlying the silicide.